1. Field of the Invention
The present invention relates to behavioral synthesis technology. More specifically, it relates to a behavioral synthesis apparatus, an automatic behavioral synthesis method, and a behavioral synthesis program including loop processing.
2. Description of the Related Art
A behavioral synthesis apparatus of a computer system synthesizes a register transfer level (RTL) hardware description (hereafter referred to as ‘RTL description’) from a behavior description using a method described forthwith. A control data flow graph (CDFG) is created based on circuit behavior descriptions. ‘CDFG’ denotes a graph specifying the order of calculations and data accesses for a circuit behavior written in the behavior description. Steps of executing the calculations in the CDFG are determined. Registers that store data and operational units that execute the calculations in the CDFG are also determined. Afterwards, data paths and control circuits such as state machines or the like are generated so as to synthesize the RTL descriptions.
In a case where loop processing is written in the behavior description loops many times, the number of calculations to be executed in the loop increases. Therefore, the time required for loop processing by synthesized circuits increases. Accordingly, it is necessary to reduce time for loop processing in order to synthesize circuits that operate at high speed.
Loop processing is typically carried out as pipeline processing. Accordingly, synthesis of RTL descriptions for high-speed execution of pipeline processing is necessary to reduce time for loop processing.
A method of synthesizing a pipeline circuit by generating a CDFG including a control unit that assigns each loop processing to stages of pipeline processing (hereafter simply referred to as ‘stages’) and controls processing in each stage is available as a method of synthesizing RTL descriptions including pipeline processing. However, the above-mentioned method fails to include a behavioral synthesis method for behavior descriptions of multiple loop processing.
‘Multiple loop processing’ performs another loop processing while a loop is processing. Another loop processing executed during a current loop processing is hereafter referred to as ‘internal loop processing’. Furthermore, a loop processing including internal loop processing is referred to ‘external loop processing’. In the related art, a pipeline circuit for executing external loop processing is synthesized after the internal loop processing is expanded. In other words, the internal loop processing is not carried out during pipeline processing. Therefore, the number of cycles (pipeline pitch) necessary for a single stage of pipeline processing is increased. As a result; reducing the working speed of the circuits synthesized according to the behavior descriptions, including multiple loop processing, has been a problem.